The present invention relates to a bipolar MOS logic circuit, in which bipolar transistors are combined with MOS field effect transistors, and in particular to a static and a dynamic logic circuit as well as a semiconductor integrated circuit of bipolar CMOS (complementary MOS) type, which are suitable for a low voltage operation.
The so-called Bi-CMOS logic circuit, in which both bipolar transistors and CMOS transistors are used, is well known, such as in U.S. Pat. Nos. 4,588,234, 4,616,146, 4,638,186, 4,769,561, and 4,779,014.
FIG. 9A shows a Bi-CMOS logic circuit disclosed in U.S. Pat. No. 4,769,561 described above. Since this circuit has advantages of low input capacitance, high output driving power, low power consumption and high speed, it is widely utilized in logic integrated circuits (LSI) and memory LSIs. However, this circuit has a problem in that the advantage of high speed described above is quickly lost for a power supply voltage around 3 V, although the advantages described above can manifest themselves for a power supply voltage around 5 V. The deterioration in the speed accompanied by the decrease in the power supply voltage is produced principally as a result of a substantial increase in the delay time of the fall of the output signal, as indicated in FIG. 9B. FIG. 9C indicates the dependence of the delay time with the fall of the power supply voltage, in which the full line represents such a dependence on the power supply voltage for a CMOS logic circuit and the broken line the same for a Bi-CMOS logic circuit. As clearly seen from the figure, in a prior art Bi-CMOS logic circuit, the delay time increases quickly, when the power supply voltage is lowered to a value around 3.5 V, and the usefulness thereof as a high-speed operation logic is lost for a power supply voltage around 3 V.
The principal cause which lead to the deterioration in the speed include the following: the base current in NPN transistor 902 (FIG. 9A) decreases quickly as a result of a decrease in the amplitude of the input signal accompanied by the lowering in the power supply voltage, the rise in the source potential in N channel MOS transistor (hereinbelow called simply NMOS transistor) 905 due to the base-emitter voltage V.sub.BE, which is peculiar to the Bi-CMOS circuit, the decrease in the source-drain voltage V.sub.DS in the NMOS 905, etc.
FIG. 10 shows a circuit disclosed in U.S. Pat. No. 4,558,234 stated above. In this circuit an NPN transistor (hereinbelow called simply NPN) 1001 is used for pulling up the output and an NMOS 1002 for pulling down the output. Since an NPN transistor is not used as the pulling down transistor in this circuit, a quick decrease in the speed is not produced even for a power supply voltage around 3 V. However, since an NMOS transistor is used as the pulling down (pull-down) transistor, in the case where a load having a large capacitance is driven, the delay time in the fall of the output is long. If it is attempted to increase the driving power by increasing the conductance of the NMOS transistor, the gate capacitance increases, which lowers the speed of the circuit in the preceding stage. Further, it has another drawback in that the effective load is increased by the drain junction capacitance itself.
FIG. 11 shows a circuit disclosed in U.S. Pat. No. 4,638,186, whose principal purpose is to reduce the delay of the fall in the Bi-CMOS logic circuit. This circuit is identical to that indicated in FIG. 9A, except that an NMOS transistor 1107 is added thereto, and works as an inverter circuit. The drain of an NMOS transistor 1107 is connected with the input terminal 1111, the gate is connected with the output terminal 1120 and the source is connected with the base of an NPN transistor 1102. Now a case where the input is changed from "0" to "1" is considered. The output 1120 is at first at the level "1" and the NMOS transistor 1107 is turned on. Consequently the base current flows from the input to the NPN transistor 1102 through the NMOS transistor 1107, which turns on the NPN transistor 1102. Since this base current has added to it a current from another NMOS transistor 1105, the resulting base current of the NPN transistor 1102 is increased, which has an effect of reducing the delay of the fall of the output. However, since this circuit is such that the base current of the NPN transistor 1102 flows from the input terminal 1111, it has a problem in that the input impedance is low, which leads to another problem that the load viewed from the driving circuit in the preceding stage is increased. Further, since the gate of the NMOS transistor 1107 is connected with the output terminal 1120, the drain current is lowered rapidly with the fall of the output and therefore the full extent of the result expected, cannot be manifested.
FIG. 12A shows a circuit disclosed in U.S. Pat. No. 4,716,310 for increasing the switching speed of the pulling down (pull-down) NPN transistor In this circuit an NPN Q.sub.1 is driven by a PMOS transistor Q.sub.3 and the pulling down transistor Q.sub.2 is driven by NMOS transistor Q.sub.4 and Q.sub.5. The NMOS transistor Q.sub.4 and Q.sub.5 are connected in series between a power supPly V.sub.H and the base of an NPN transistor Q.sub.2, the gate of NMOS transistor Q.sub.4 is connected with the input signal terminal IN and the gate of NMOS transistor Q.sub.5 with the outPut signal terminal OUT.
One of the problems arising from such a circuit is that since there exists no means for discharging the base of transistor Q.sub.1, an undesirable collector current (corresponding to the hatched part in the related waveform indicated by I.sub.Cl in FIG. 12B) flows through the transistor Q.sub.1, which should be originally turned off, at the fall of the output OUT and that in this way the falling speed of the output is lowered and at the same time power consumption is increased.
Another problem is that since the gate of the NMOS transistor Q.sub.5 is connected with the output OUT, and noting that the transistors Q.sub.5 and Q.sub.2 are turned off when the "0" level V.sub.OL is lowered to V.sub.OL=V.sub.L +V.sub.BE (Q.sub.2)+V.sub.TH (Q.sub.5), as indicated by the waveform OUT in FIG. 12B, the output is not lowered sufficiently to "0" and the level required as a logic circuit (for example, logic "0" level) cannot be secured.
Still other Bi-CMOS circuits, by which attempts to shorten the delay time in the fall, are disclosed in FIGS. 10 to 20 in U.S. Pat. No. 4,779,014. In FIG. 10 thereof, NMOS transistors 18, 19 and 20 constitute a pulling down base current supplying circuit, among which the NMOS transistors 18 and 20 are newly added, in order to increase the base current. This circuit, however, has following problems;
1) The number of NMOS logic elements employed between V.sub.OUT and the base of an NPN 15 is twice as many as that required in a prior art equivalent circuit. That is, 2N NMOS transistors are necessary for N input gates (N being an integer). PA1 2) Since the NMOS transistor 18 is added, the circuit between V.sub.OUT and the NPN transistor 15 includes the NMOS transistors 18 and 19 connected in series and therefore the base current supplying power of the NPN 15 is reduced to about a half. PA1 3) The control transistor 19 is an NMOS transistors. Consequently, the gate just before the fall of V.sub.OUT is at the level "1". At this time the source potential of the NMOS 19 is (V.sub.OUT -V.sub.th) and the NMOS 19 is in a high impedance state, which is close to that observed, when it is turned off.
For this reason, since no current can flow through the NMOS 19, unless the source potential is lowered to a value below (V.sub.OUT - V.sub.th), the supply of the base current passing from the power supply to NMOS 18 through NMOS 19 is delayed. Consequently, this circuit can contribute almost nothing to the shortening of the delay of the fall of the output V.sub.OUT.
Further, since the bias between the gate and the source of the NMOS 19 becomes rapidly decreased together with the fall of the output V.sub.OUT, there is a problem that the added base current is decreased rapidly and therefore no substantial improvement in the operation speed can be expected.
Now, in order to solve problems involving the lowering of the breakdown voltage of elements accompanied by the decrease in the size of semiconductor devices and the increase in the power consumption accompanied by the increase in the integration, the tendency of lowering the power supply voltage has become more and more inevitable. Therefore, a Bi-CMOS logic circuit capable of manifesting performance as high as that obtained heretofore even with a low power supply voltage is strongly desired.
As explained above, the prior art Bi-CMOS logic circuit has a problem in that it cannot be used as a high speed logic circuit of in connection with the development and demands of the next generation devices, because the switching speed is rapidly lowered, when the power supply voltage is lowered to a value around 3 V.